On June 14, Elon Musk said Tesla’s next‑gen AI6 chip is progressing through engineering review and, based on yield trends, could set a new record for usable compute per wafer. The current‑gen AI5 has taped out and is scheduled for H2 2027 production. AI6 is expected to enter production in H2 2028.

AI5 delivers 5x the compute of the two AI4 chips combined in current vehicles. AI6 doubles AI5’s performance – not just a node shrink but a full overhaul of processor and memory architecture.

Starting with AI5, Tesla’s new hardware platforms significantly expand memory. (Current FSD already maxes out AI4’s memory and bandwidth.) Both AI6 and its follow‑on AI6.5 adopt an innovative design: nearly half the TRIP compute accelerators are tightly coupled with high‑speed SRAM , allowing complex operations to run from cache without waiting on main memory. Main memory is upgraded to LPDDR6 for higher speed.

Tesla signed a $16.5 billion long‑term foundry deal with Samsung , which will build AI6 on its 2nm process at Samsung’s new Texas fab through 2033. Tesla also collaborates with Intel and SpaceX on the TERAFAB vertical integration chip project.

AI6 will power robotaxis, FSD for consumer vehicles, Optimus humanoid robots, and space data centers. It will first be deployed in Optimus and training superclusters before reaching consumer cars.

ICgoodFind: Tesla’s AI6 targets per‑wafer compute records with SRAM‑coupled TRIPs and LPDDR6 – a true architecture revolution backed by Samsung 2nm.